From Wikipedia, the free encyclopedia.
MIPS is an acronum for Microprocessor without Interlocked Pipeline Stages, a microprocessor architecture developed by MIPS Computer Systems Inc..
The MIPS CPU family was one of the most successful and flexible CPU designs throughout the 1990s and has found broad application in embedded systems, Windows CE devices, SGI workstations, and Cisco Internet routers. The Nintendo 64 video game console uses a 64 bit MIPS processor.
The MIPS CPU features a five stage CPU pipeline to execute multiple instructions at the same time. The CPU has 32 registers, from which two serve special purposes, the rest being available to generic use, regulated through ABI conventions. Popular compilers that target the MIPS architecture include the MIPSPro Compiler and GCC. Four backward-compatible revisions of the MIPS instruction set exist, named MIPS I to MIPS IV. Because the designers created such a clean instruction set (see Instructions), computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs like HP Precision Architecture and Alpha.
The early MIPS architectures were 32 bit implementations (generally 32 bit wide registers and data paths), later versions were 64 bit implementations.
In 1984, researchers at Stanford University created the first MIPS processor. The first commercial MIPS CPU, model R2000, was released in 1985. In 1987 the successor, the R3000 CPU was released. It had cache design problems and led to the development of the R4000 and R6000 MIPS CPU series. The R4000 CPU turned out to be a commercial success when introduced in 1991. It had features that broke new ground: a true 64 bit architecture, a real 64 bit instruction set and 64 bit registers, huge on-die caches, and high clock frequencies. Later designs reused the R4000 core, namely the R4400 (1993), R4600 (1993) and R4300 (1995) CPUs. In 1996, MIPS introduced the R10000 CPU for high-performance applications and the low-power, inexpensive R5000 CPU suited for embedded systems.
The R5000 had certain optimizations over the earlier R4400 and R4600 that allowed faster graphics processing; mostly, this amouted to the FPU being optimized for single precision. R5000 based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement.
The R8000 (1994) was a two-chip set optimized for floating point performance. The first chip was an integer unit with performance comparable to the R4400 and the second chip was a highly advanced FPU which performed like the R10000, which would not be introduced for another few years. The R8000 powered SGI's Power Challenge compute servers in the mid 90's and later became available in the Indigo2 Impact workstation. Its limited integer performance and high cost dampened appeal for most users. However, its FPU performance fit scientific users quite well. It was phased out with the R10000's acceptance into the market. The R10000, with a simpler FPU, achieved similar FPU performance through higher clock speed and featured much better integer performance, widening its appeal. It employed an ANDES architecture.
The more recent R12000 and R14000 are fairly similar to the R10000, with the exception of being on a smaller process, having a higher clock, and supporting faster memory and external cache interfaces. They are evolution, not revolution. In the past, SGI promised a more complex R8000 style FPU for later R-series (R16000?), but their current plans are not clear. One thing that is clear is that MIPS will be their line of choice much longer than expected, since Itanium has been a disappointment and IRIX is still more advanced than Linux.
Patterson and Hennessy: Computer Organization and Design. The Hardware/Software Interface. Morgan Kaufmann Publishers. ISBN 1-55860-281-X
This book about computer design in general, and RISC in particular takes its examples directly from the MIPS architecture. No wonder, since Hennessy was an early collaborator in the Stanford project which became MIPS.